by W.M. Beynon and J.N. Buxton
Department of Computer Science
University of Warwick
Coventry CV4 7AL
ENGLAND
July 1979
This document describes the third version of the "Introduction to Computer Science" computer. The machine has been designed for use in introductory courses to give students some appreciation of elementary hardware and of machine level programming. It is a 16-bit word computer with three main registers and an order code of some 30 orders. The machine is implemented by a simulation program (written in extended Algol 60) on the B6700 system. The simulation provides some basic software consisting of a loader and post-mortem system. The language accepted by the loader and described below is basically machine code with mnemonic function codes.
In general the functional operation specified in an order takes place using a register as one operand as specified in the order, and a further operand or store location specified by the A and M fields in the order. Four modes may be specified by M, with the following meaning:
M = 0 | Literal: the A-field is taken as a positive operand in the range 0 to 511. |
M = 1 | Direct: the A-field addresses the operand in the first 512 words of the store. |
M = 2 | Indexed: the address of the operand in store is given by the contents of X plus the value of A. |
M = 3 | Indirect: the address of the operand is held in the store location addressed by A. |
The store address register is not directly addressable to the user. It is used in the implementation to hold the "effective address" of the store location as determined for modes 1, 2 and 3 above.
A 16-bit register which denotes the next word of store as a machine order to be fetched, decoded and executed. It is incremented by one immediately after fetching an order and before executing it.
When a word has been fetched from store it is placed in this 16-bit register. The register has three fields known as the function, mode and address fields respectively:
F-field 5 bits |
M-field 2 bits |
A-field 9 bits |
bit 15... | ...bit 0 |
A 16-bit signed register used in particular in indexed address mode as described above.
A is the main 16-bit signed register used for arithmetic and logical operations. For operations which require a double-length operand or result, the 32-bit extended register BA is used. The B register is not directly addressable and its contents can be accessed separately only by the EXC order.
There are three condition code bits to indicate register zero, negative or overflow conditions. The zero and negative condition code bits are set to indicate the status of the relevant register after any order with function code 00 through 17 has been obeyed. The overflow condition is set by the arithmetic operations 04 through 07, and by DIV, in the event of too large a quotient or attempted divide by zero. (Note that orders 10 and 11 set the condition codes exactly as the 06 and 07 orders respectively but without changing the contents of A).
The orders 30 and 33 transfer control depending on the condition code settings.
The four topmost store addresses refer to pseudo-locations - the "bus addresses" - which behave as input/output registers. An attempt to read from location 32764 produces the next input stream character as an unsigned 8-bit number, right-justified, as the operand using B6700 character coding. Store operations to this "address" are inhibited. Conversely, a store operation to 32765 sends an 8-bit character to the output stream. "Addresses" 32766 and 32767 behave similarly for decimal numbers.
00 | LDA | load operand to A |
01 | LDX | load operand to X |
02 | STA | store A in addressed location; mode 0 invalid |
03 | STX | store X in addressed location; mode 0 invalid |
04 | ADA | add operand to A |
05 | ADX | add operand to X |
06 | SBA | subtract operand from A |
07 | SBX | subtract operand from X |
10 | CPA | compare operand with A, as for 06 but A left unchanged, CC set |
11 | CPX | compare operand with X, as for 07 but X left unchanged, CC set |
12 | ANA | logical AND operand with A |
13 | ANX | logical AND operand with X |
14 | ORA | inclusive OR operand with A |
15 | ORX | inclusive OR operand with X |
16 | NTA | complement A, operand ignored |
17 | NTZ [sic] | complement X, operand ignored |
20 | SLL | shift BA logically left, operand (necessarily literal) specifies shift length |
21 | SLR | shift BA logically right, operand (necessarily literal) specifies shift length |
22 | ||
23 | ||
24 | MPY | multiply A by operand, result double length in BA |
25 | DIV | divide BA by operand, result in A, remainder in B |
26 | ||
27 | EXC | exchange A and B, operand ignored |
30 | JCP | copy effective address to program counter if neither Z not N set |
31 | JCN | copy effective address to program counter if N set |
32 | JCZ | copy effective address to program counter if Z set |
33 | JCV | copy effective address to program counter if V set |
34 | JMP | copy effective address to program counter unconditionally |
35 | SBR | copy program counter to X and effective address to program counter |
36 | DXT | decrement X by 1, if X does not equal 0 then copy effective address to program counter |
37 | HLT | cease execution, return to Initial Orders |
The order SBR is used as a convenient and standard means of subroutine entry. This order stores the "return address" in X. Subroutines must preserve this address and restore it if X is used. A standard return order is then possible by the "indexed jump": JMP 2 0
When first switched on the machine begins to obey the "Initial Orders". These may be regarded as software private to the system and working in store concealed from the users. Essentially the software reads in a "document" line-by-line from the input device. Lines of input of the following kind are accepted:
@p:a where p is a page number (necessarily 0 or 1) and a is the address of a location in the range 0 <= a <= 511, specified as a 3-digit octal number.
>p:a where p is a page number (necessarily 0 or 1) and a is the address of a location in the range 0 <= a <= 511, specified as a 3-digit octal number.
This terminates execution of the initial orders, and instructs the ICS3 computer to obey the order whose address is specified by the directive: normally this represents the start point of the program just loaded.
Any data required by the ICS3 computer during an execution must be supplied on the lines which follow directly the "execute" directive (one data item per line). A data item consists of either a character following by a space or a signed decimal constant.
In the event of failure in the execution of the ICS3 computer, an error message will be output in the format ***....., the store will be dumped, and exit from ICS invoked.
#p:a - q:b where p and q are page numbers (0 or 1) and a and b are the addresses of locations in the range 0 <= a, b <= 511, specified as a 3-digit octal numbers.
The contents of all store locations in the specified range are printed out in several different formats:
and, where appropriate:
Contents of machine registers and bus addresses are also displayed. Note that store locations which contain zero are suppressed in any dump.
?
This directive is used to switch on (or switch off) a trace facility, usually for debugging purposes. When trace is set, each execution of an order by the ICS3 machine is monitored.
% n where n is an unsigned decimal integer.
This directive resets the maximum number of ICS orders executed in a run before automatic abortion.
The machine code orders are of three types.
(a) null-address orders viz. NTA, NTX, EXC, HLT (mnemonic), 16, 17, 27, 31 (octal)
(b) literal orders viz. SLL, SLR (mnemonic), 20, 21 (octal)
(c) remaining orders, for which both mode and address are specified.
Class (c) orders have the three field format f m a, where f is either a function mnemonic or valid octal function code, the m-field is 0, 1, 2 or 3, and the a-field consists of a three-digit octal number.
Class (b) orders, in which the a-field is always interpreted literally, require no m-field, and must be specified in the two field format f a.
Null address orders require neither m- nor a-field.
While the machine is obeying initial orders, any valid machine code order encountered is loaded into store at the location currently indicated by the word pointer, which is incremented by l after any load operation.
Valid constants are loaded into store at the word indicated by the loading pointer. They are of two types:
(a) Integer constants, written as signed decimal numbers in the range -32768 <= n <= 32767. Eg +95, -318.
(b) Character pair constants, which are written within quotes, and are loaded as 16-bit words comprising the two 8-bit B6700 character codes. Eg "AB".
$
Exit from ICS3 system, and end of job.
Any characters following (and on the same line as) a valid directive or machine code order will be taken as comment.
Any line format other than those specified above will be detected by the initial orders, and the message * LOADING ERROR *... output. Ill-formatted lines are otherwise ignored.
The internal representation of EBCDIC coded characters used on the B6700 computer is given...
In order to run the ICS3 simulation program from cards a job-deck of the following type is required: ...
Errors encountered by the ICS3 machine whilst it is obeying initial orders are indicated by error messages prefixed by "* LOADING ERROR *". Lines invoking such errors are otherwise ignored.
ICS3 recognises six loading error conditions. These are listed below, together with typical examples of their occurrence.
Errors which lead to failure in execution of the ICS3 machine are indicated by error messages prefixed by "***". Execution errors invoke an ICS3 store dump, followed by job termination.
They are of three main types:
Execution of the ICS3 machine also terminates if the permitted number of machine cycles (default 100) is exceeded, or two consecutive zero (eg LDA 0 000) orders are encountered.
Document re-typed into HTML from an original 1979 typescript by Ashley Ward in May 2002.