Year 3 ambassador: Ken Diep
This 15 CATS module is one of the third year modules for:
To introduce students to the principles and practice of designing digital electronic circuits, with a focus on field programmable gate array implementation, including the tool flow, architecture, testing, and design for performance.
By the end of the module students should
- Through the practical use of the Verilog hardware description language (HDL), consolidate understanding of the theory of combinational and sequential circuits and how these combine in the design of digital computing circuits.
Evaluate the digital design flow as currently practised professionally in industry, with reference to field programmable gate arrays, and at a more general level, to custom application specific integrated circuits.
Analyse how mathematics is performed in custom circuits, and how simple units can be combined to implement complex compute datapaths.
- Devise a testing strategy and design a testbench to evaluate the functional correctness of a circuit using the testing features of the Verilog HDL and a professional standard simulator.
- Reason about the performance of synchronous digital circuits, based on the timing of basic components, and how pipelining affects performance, and how this differs from measuring the performance of software running on processors.
Recap of combinational and sequential circuits: gates, multiplexers, encoders, decoders, latches, D flip-flop, registers, shift registers.
Design with hardware description languages: (Verilog) module definitions, gate-level circuits, assign statements, behavioural combinational descriptions, behavioural synchronous descriptions.
Design flow and FPGA architecture: basic circuit synthesis, FPGA logic blocks, hard blocks, I/O, mapping to FPGA blocks, placement and routing, configuring FPGAs.
Testing digital circuits: basic Verilog testbenches, self-checking testbenches, file I/O for input/output vectors, testing strategies.
Arithmetic circuits: limits of ripple adders, carry-lookahead adders, multipliers, fixed-point data representation and resulting errors, floating point circuit complexity.
Timing and pipelining: basic combinational timing characteristics, timing of synchronous components, computing circuit timing performance, pipelining for improved performance, hazards, race conditions, and metastability.
Processors and I/O: basic structure of a processor and how this relates to performance, integrating peripherals over UART, SPI, I2C, and faster serial standards, computing data rates for these standards.
This module includes 20 hours of lectures, 2 hours of revision classes and 12 hours of laboratory sessions.
Required self-study: 116 hours
A 15 Credit module: 70% assessed via a 3 hour examination paper and 30% assessed via a design assignment (2000 words).