Content and teaching | Assessment | Availability

Module content and teaching

Principal aims

To develop a student’s ability in digital design to the level of designing high performance software/hardware embedded systems using hybrid FPGA reconfigurable devices combining processors and reconfigurable hardware fabric.

Principal learning outcomes

By the end of the module the student should be able to: • Apply the more advanced features of FPGA architectures in high performance embedded systems design. • Design a hardware accelerator for a complex algorithm by evaluating its parallelism and arithmetic requirements. • Integrate a hardware accelerator with a processor and design the necessary software and hardware communication infrastructure. • Apply practical knowledge of hardware design at the register transfer level and use high level synthesis.

Timetabled teaching activities

20 x 1 hour Lectures 7 x 2 hours Laboratories (un-assessed, support design assignment) 2 x 1 hour Revision Classes Total 36 hours

Departmental link

www2.warwick.ac.uk/fac/sci/eng/eso/modules/year3

Other essential notes

Advice and feedback hours for answering questions on the lecture material (theory and examples) and past examination questions. Student must pass the examination and the coursework.

Module assessment

Assessment group	Assessment name	Percentage
15 CATS (Module code: ES3F1-15)
D1 (Assessed/examined work)	Design Assignment (10 pages)	40%
	2 hour examination (Summer)	60%

Module availability

This module is available on the following courses:

Core

• Undergraduate Computer Systems Engineering (G406) - Year 3
• Undergraduate Computer Systems Engineering (with Intercalated Year) (G407) - Year 4
• Undergraduate Computer Systems Engineering (G408) - Year 3
• Undergraduate Computer Systems Engineering (with Intercalated Year) (G409) - Year 4

Optional Core

N/A

Optional

N/A