Author: Hawk

Signal-to-Noise Ratio

Today, when communication systems have become so widespread and such an essential part of our lives, more power than ever is used for data transmission. Needless to say that by improving the electrical efficiency of these systems a considerable amount of energy can be saved.
One of the key factors that determine the maximum possible efficiency of a communication system is the noise present in the transmission medium. A significant parameter that describes the minimal possible power consumption of a system is its signal-to-noise ratio. For each given system there is a minimal practically achievable noise power, and depending on its encoding mechanism there is a minimal necessary signal-to-noise ratio to make it work (e.g. 10dB, 20dB or more, analogue systems are less noise resistant than digital). Given these two the minimal necessary signal power can be determined which is directly proportional to the system’s power consumption.

The aim of this project is to take a digital PPM (pulse position modulation) system, which is already known as one of the more power-efficient transmission mechanisms and reduce its minimal signal-to-noise ratio (make it more noise resistant) so that it could be operated with less power. To do this a simple 4 PPM encode-transmit-decode mechanism was built using shift registers and another one that makes use of an analogue mechanism with sample-and-hold circuits and a comparator was created.

How PPM works:
When transmitting a string of digital data (ones and zeroes) by PPM, it is split into packets (in this case of 2 data bits per packet), each one is separately encoded into a PPM packet and then sequentially transmitted along the wire/optical channel at the other end of which they are decoded and restored to the original string. Each PPM packet is split into a certain number of time slots (in the given case 4) and only one time slot per packet contains a logical high value. The encoder and decoder obviously need to have the same PPM packets associated with corresponding data packets but the choice of these combinations is arbitrary. Because the logical high on the PPM signal is present for a smaller length of time than on the original one, less power is consumed when transmitting in PPM (in this case 50% less power consumption but it can be further reduced by increasing the number of time slots, e.g.. 8 or 16).

To make the system more noise resistant another decoder is made, in this one analogue components are used as well as digital and instead of reading each PPM time slot separately as “high” or low it compares them to each other and declares the one with the highest voltage “high” and the others “low”. The PPM signal is fed into an integrator which acts to the average voltage over across each time slot (it is reset at the beginning of each new time slot) and a series of 4 S&H (sample and hold) circuits which pass this averaged time slot voltage from one to the next at clock frequency, the final bit is the comparator that compares the outputs of the second and fourth S&H circuits. The feedback AND gate ensures that the S&H #4 keeps the highest voltage value encountered in the 4 slots and so the comparator compares the highest value this far to the incoming one. The original signal can then be decoded by storing the comparator outputs in a shift register and applying the correct logic (similar to that in the first decoder). Multisim does not allow to simulate S&H circuits but the schematic representation of this circuit can be seen below and it has been placed on the breadboard.
This decoding mechanism is a lot more noise resistant as the voltage difference between PPM slots instead of overall voltage determines the result and impossible PPM code combinations (more than 1 PPM time slot high) are dropped off automatically substituting them with the most likely possible one.

Below is a Multisim circuit that contains a pseudorandom signal generator (generates a data string that appears random in nature and can be considered such for the purposes of the experiment but is actually repeatable which allows to reconstruct the data flow later exactly), three clock mechanisms derived from one 555 timer, an encoder that consists of two shift registers and logic, and a decoder that also consists of two shift registers and logic. This setup is relatively simple and straightforward, to the left below the simulated oscilloscope when the simulation is run can be seen (original signal in yellow, PPM signal in light blue, and decoded signal in purple), it can be seen that there is a time delay between the original and decoded signals, this is because encoding and decoding is done in packages, so the encoding and decoding mechanisms have to wait for the entire package to arrive before it can be encoded/decoded.
Although this decoder circuit as any has a certain degree of noise resistance, it has not been built to be noise resistant, and if the noise in the signal reached the “on” voltage of the decoder’s input, which would be between 1 and 2 volts meaning a signal-to-noise ratio of about 4 or 12dB, it would perceive noise as the actual digital signal and see a digital “high” in slots meant to be “low” thus giving an erroneous result and effectively stopping to work as intended.
In the noise source the avalanche breakdown in a reverse biased Zener diode is amplified in two stages, this gives white noise with a bandwidth of several hundred megahertz.

Results and conclusions:
The most important conclusion is that digital systems’ minimal acceptable signal-to-noise ratio and hence noise tolerance can be significantly improved when supported by an appropriate analogue circuit. Experiments on the circuit showed that the analogue circuitry method was more robust than the digital circuitry one and the integrator in combination with sample and hold chips give a good representation of the voltage value over the slot’s time period. Work still continues on the circuit breadboarding and it is possible that it will get soldered onto a chip.

Work experience:
This project gave insight of what it is like to design and build electronic circuitry, which I had only experienced in very controlled environments this far. The lack of strict boundaries and tight supervision made it more challenging but in this it gave room to make mistakes and being forced to solve them on my own, and I think that solving mistakes is the most valuable skill this project has given me. I learned to overcome some of the difficulties electronic engineers encounter in their work and to accept that more time needs to be spent troubleshooting than designing the circuitry. The experience gained in this project should prove invaluable when doing the 3rd year project as it has shown me which details to pay more attention to and given a better understanding of how to manage time. I also gained deeper knowledge of how PPM works and strengthened my skills in designing logic.

Project sponsored by the EPSRC in association with the Graduate school.

Andris Egle (Electronic Engineering year 3)
Project supervisor: Dr. Mark Leeson

Acknowledgements:
I would like to thank Dr. Leeson for the support and advice in both the design and implementation stages of the project, which served as a base for my work.
Many thanks to URSS and EPSRC without which this project would not have been possible.

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