The SaSHa project consist of six work packages.
WP1 is concerned with the management of the project, while WP6 will oversee all dissemination and communication activities.
WP2, Simulation, will inform and shape every prior WP, defining in simulation the optimal material characteristics, the device structure and fabrication process, and the requirements for radiation hardness.
WP3, Materials, will use state of the art materials processing and characterisation technologies, including wafer bonding, to perfect the formation of intimate Si on SiC wafers, delivering these substrates for processing.
After initial trials, WP4 fabrication, will take the substrates and the device designs and produce the devices using state-of-the-art clean room fabrication processes.
WP5, reliability, will then test the credentials of the devices including the use of an ESA accredited cyclotron to test their immunity to radiation.
The simulation WP will be aimed at developing advanced TCAD models for simulation of radiation-hard high voltage power devices fabricated on Si on SiC substrates suitable for space applications. The final models will be further optimized and fine-tuned using the feedback from the measurements performed on fabricated devices. Optimized models will be able to predict behavior of new devices designed and fabricated using Si on SiC technology (TL2 to TL4).
Development of novel Si/SiC substrate is the key to the production of the high temperature transistors. The novel bonding processes will be improved, and the physical characteristics of the layers explored, especially the critical materials interface. Si substrate thinning post-bonding will also be developed.
The aim of the device fabrication work package is to develop the first Si/SiC power electronics transistors, implementing the designs developed within the Simulation WP and using the novel Si/SiC substrates developed within the Materials WP.Within Warwick University’s state-of-the-art clean room processing facilities Si/SiC test structures, diodes and CMOS transistors will be produced and tested before full LDMOS and LIGBT Si/SiC transistors rated to 200 and 600V will be produced. Extensive characterisation activities will qualify the devices and feedback the information to the simulation WP1 in an iterative loop that will produce two generations of improving Si/SiC transistors.
The Si/SiC devices are being designed to work in the harsh environment of space where there are extremes of temperature (typically -200 to 300°C) and significant background radiation. In this WP, these extreme conditions will be recreated in the lab and the reliability of the devices pushed to their limit. The objective is to understand how well the new devices will perform in these conditions compared to the current state-of-the-art.