Call for Papers

Journal of Information Law and Technology/
European Journal of Law and Technology

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Protecting Open Source Hardware?

Protection for software produced under the GPL is well known and shown to be successful, based upon copyright protection and licensing. It is not so obvious that the same model can be moved over to hardware, since historically engineers have been allowed to reverse engineer products at will, so long as they are not protected by patents etc. The heart of the problem, so far as opens source hardware goes, is that the open source philosophy relies on the key principle that you are free to use my work, but only if you subsequently share your derived work, so the benefit continues. It relies on a suitable legal framework to enforce this "contract".

Current developments in hardware are moves away from the traditional ‘Von Neumann’ architecture to multi-core, parallel processing forms and also system-on-a-chip approaches. These are very complex and difficult to produce and this is where companies seek to make money. Protection is important since special purpose chips are now part of almost every device being manufactured and markets can be large. It is not clear how best protection for these can be enabled – earlier forms such as ‘mask protection’ are no longer so relevant when the whole process of design and manufacture is through special purpose languages.

The question we are setting in this call for papers is: what is the best method to enforce the open source philosophy for hardware, to ensure that contributions based upon the work of others remain open for others to develop.

One example of the attempt to produce relevant licensing is the TAPR Open Hardware License - http://www.tapr.org/OHL which has been discussed by the open access community.

However, since ‘Open Source Hardware’ is relatively unexplored in terms of legal issues, articles will be important contributions to the legal debate. We are seeking papers which look into the relevant issues and which might help to move the open source model into this new arena. Topics could include:

1. What are the issues which separate software and hardware open source models?
2. What elements of the GPL are appropriate or not appropriate for protecting hardware developments from freeloading?
3. Is a new ‘Hardware GPL’ model required?
4. Is hardware protection possible through the programming which underpins development?
5. What problems arise from ‘contractual’ models of protection?
6. Is it possible to develop an ‘international’ consensus on protection?
7. Can hardware – where it is not subject to patent – ever be protected anyway?

These, of course, are the issues which lawyers looked at in terms of software in the 1980s. The developments in hardware (‘chip’) protection now mean that the same kinds of questions asked then, must be asked now, as the economics and manufacturing of chip technology moves into a new phase.

Technical advice will be available to legal authors to ensure full understanding of these issues. An overview of current design and manufacturing contexts is attached.

If you wish to contribute to the Special Edition, then please contact Philip Leith at p.leith@qub.ac.uk

More Information

1. Technical Background

There are two types of logic silicon chip in widespread use:

(1) application specific integrated circuits (ASICs) and
(2) programmable hardware chips of various types.

In addition to these there are a number of different types of memory chips, which can be divided into (1) those that lose their memory when power is turned off (the Dynamic Random Access Memory (DRAM), and (2) those which retain their memory when power is turned off (Static Random Access Memory (SRAM) and flash programmable memory). Typically software programs are stored in the memory chip(s) and their behaviour executed on the logic chip.

ASICs are a one-off manufacture. Once you have made one, its hardware logic is fixed. Variations in behaviour are through software running on the ASIC. This is achieved by connecting the ASIC to memory holding programs which drive the logic of the ASIC.

The most common programmable chip is the Field Programmable Gate Array (FPGA), but you also come across the Complex Programmable Logic Device (CPLD), which despite the name is simpler. The obvious advantage is that the hardware can be changed to perform different functions under different circumstances.

The advantages of ASICs are low cost with high volume, low power consumption (so essential for the likes of mobile phones) and ability to cope with huge designs. The big disadvantage is the huge up-front manufacturing cost - up to $50M for the most complex modern chips, although it can be less than $50k for a simpler design.

The advantage of FPGA is its low up front cost, which is particularly appealing for small volume products. Entry level boards containing an FPGA, memory and peripheral logic drivers cost less than $50. The disadvantages are the far higher power consumption and the limited size of design (although still fairly large) that can be used.

2. Manufacturing ASICs

ASICs are made by building up successive layers of semiconductor, insulator and metal on a wafer of ultra pure silicon. Each layer is built using a process akin to developing a photograph. A layer of photo-sensitive chemical is spread on the silicon wafer. Light is shone through a mask, which "fixes" the photo-sensitive chemical where it lands. The unfixed chemical is then washed away, leaving the underlying silicon exposed. The new layer is deposited on the exposed silicon (typically as a gas at high temperature). The fixed chemical can then be dissolved and the whole process reapplied for another layer.

The costs arise from the precision required. The features on the latest chips can be as small as 20-30 nm (about 100 atoms) and some of the layers only 5 atoms thick. Each layer must be aligned accurately, and there can be typically 30+ layers. The deposition may require temperatures over 1000 ˚C accurate to 0.25 ˚C. The masks must be accurate over silicon wafers which are 30 cm in diameter. Light has far too long a wavelength (400-700nm) to be used with such masks, so extreme UV or X-rays must be used, the latter requiring a synchrotron to generate. Not surprisingly masks for such a process cost in excess of $1M.

Fortunately the costs are much lower using older versions of the technology. Reducing the feature detail by a factor of 10 reduces the logic capacity by 100, and the cost by a factor of 1000. But that's still a complex chip - it's the technology of 1999 rather than 2009.

3. Specifying the Chip Design

Originally chips were specified by drawing the masks using graphical design systems. That was soon replaced by systems which could derive the masks automatically from specifications of the electronic circuits and then later from specification of the basic logic gate operations (AND, OR, NOT, NAND, NOR etc).

Such gate level specifications are today the standard from which masks are generated or "laid out". Each gate will correspond to a small number of transistors (2-6) on the finished chip. The gates are specified using hardware design languages (HDLs, of which more later), which look like programming languages. However they have two properties: (1) they specify how the logic should be connected together, from which a physical layout can be derived to generate the mask and (2) since we know how each gate should behave, they aslo specify the behaviour of the chip, allowing us to simulate its expected behaviour for testing purposes.

When the chip has been sufficiently tested and its layout completed, the layout files can be sent for mask generation. This is known as "tape out" (the original masks were made manually using tape and then photo-reduced).

With several hundred million gates on the most complex modern chips, gate level specification is too detailed for overall logic design. It is the hardware equivalent of programming in assembler.

Approximately 25 years ago the first higher level HDLs appeared. There are two in widespread use: Verilog and VHDL (VLSI Hardware Design Language), with Verilog seeming to emerge as the more popular. There is also a modern derivative of Verilog, SystemVerilog, introduced around 5 years ago, which is starting to gain wider acceptance.

These specify logic in terms of "registers", which are blocks of logic capable of storing 1 or more bits of data. These are roughly equivalent to a variable when programming. Typically the specification will show how the contents of registers are transferred to other registers as a clock signal changes from high to low. When used in this way, the HDLs are known as Register Transfer Languages (RTL). Thus the specification of a chip may be described as being written in Verilog RTL or VHDL RTL.

These again look like programming languages. For example a fragment of Verilog might look like:

always @ (posedge clk)
begin
accumulator <= {carry_bit, adder_output}
end

This specifies that at each positive edge of the clock signal, the value in the accumulator register should be updated by concatenating the value in the carry_bit register and the value in the adder_output register.

Most modern chips are designed in this way, with designs taking up to 1 million lines of Verilog or VHDL to specify.

Synthesis tools then take the Verilog or VHDL and convert the register level specifications into gate level specifications (as described above). In fact Verilog and VHDL can both also be used as gate level specification languages, although Verilog, since it is simpler, is preferred. The typical output of a synthesis tool is a Verilog gate level specification of the chip. This can then be used for the layout process and generation of the masks.

Just as with gate level design, RTL design has a dual role (1) to specify how the logic is connected together and (2) to specify the behavior of the system, allowing simulations of the complete chip to be built.

Modern chip design relies heavily on simulation of the RTL design before sending the chip for synthesis, layout and tape out.

4. Manufacturing FPGAs (And Other Programmable Logic chips)

The design process is identical. The chip is specified using Verilog or VHDL RTL (VHDL is more common with FPGAs). However instead of synthesis to gates, layout and tapeout, synthesis is to a form suitable for programming an FPGA. This varies from manufacturer to manufacturer, but involves driving particular pins on the FPGA to reconfigure its logic. The result is the desired gates are set up on the FPGA.

5. Summary

Designs are specified in Verilog or VHDL RTL. These are tested using simulation before being synthesized to gates. The gate level design is also tested before being laid out and then taped out to a mask set. The masks are used to create the various layers required on the silicon wafer.

Author: Jeremy Bennett.

JILT 2009 (2)

 

Contents

• Editorial

Refereed Articles

• Joanne M. Kuzma
• Dexin Tian and Chin-Chung Chao
• Emir Aly Crowne-Mohammed and Yonatan Rozenszajn
• Wen Li
• Luciano Batista and Marc Cornock
• Tang Hang Wu

Commentaries

• Nehaluddin Ahmad

Book Review

• Rowena Rodrigues