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Costas Argyrides


Costas Argyrides

Research Fellow

BSc(Moscow), MSc(Bristol)

Engineering Bldg. F204
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I am a Research Fellow in the School of Engineering at the University of Warwick working on a project about “Nano Structured micro Power Smart Gas Sensors” under the supervision of Dr. James Covington and Prof. Julian W. Gardner.

I am completing my PhD (awaiting viva) at the University of Bristol working on “Error Tolerant Techniques for the Improvement of Reliability and Yield” under the supervision of Prof. Dhiraj K. Pradhan. During the first two years of my PhD I have published more than 20 technical papers and won a best paper award.

Prior to the PhD I completed an MSc in Advanced Computing and in particular on “Global computing and Multimedia” again in the University of Bristol. My thesis was entitled “A Novel Soft Error Tolerant Low Power RAM Architecture” and was conducted under the supervision of Prof. Dhiraj K. Pradhan. It was published in the “Proceedings of the 20th Annual Symposium on Integrated Circuits and System Design SBCCI ‘07″ ISBN:978-1-59593-816-9 page(s) 300-305. While a master's student I was awarded with a scholarship from Misys foundation. For my bachelor's degree I found myself in the capital of the former Soviet Union, Moscow. My undergraduate studies focused on the field of Computer Science and Informatics, at the Moscow Power Engineering Institute Technical University (MPEI-TU). At the end of my studies at MPEI (TU) I was classified in the top 10 students with excellent performance.

Additionally, I was the founder of Net-Twister LTD. Net-Twister LTD was secialised in the design and implementation of websites and software for different companies. Moreover, during my studies in Bristol I was employed by the university as a teaching assistant at several courses in the department of Computer Science and while in Moscow I was a lab assistant at MPEI (TU).


Most Recent Publications:

  1.  Costas Argyrides, Fabian Vargas, Dhiraj Pradhan, Embedding Current Monitoring in H-Tree RAM Architecture for Multiple SEU Tolerance and Reliability Improvement. IEEE International On-Line Testing Symposium, Rhodes, Greece, 3-6 July 2008
  2.  Costas Argyrides, Stephania Loizidou Himona, Dhiraj Pradhan “Area Reliability trade-off in Improved Reed Muller Coding” SAMOS VIII Workshop, SAMOS VIII, in Samos, Greece, July 21-24, 2008
  3. Costas Argyrides, Stephania Loizidou Himona, Dhiraj Pradhan “ Yield Improvement and Power Aware Low Cost Memory Chips” Workshop on Radiation Effects and Fault Tolerance in Nanometer Technologies at Computing Frontiers 2008, Ischia, Italy, May 3-5 , 2008
  4. Carlo Lisboa, Costas Argyrides, Dhiraj Pradhan, Luigi Carro, Algorithm Level Fault Tolerance: a Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms. IEEE VLSI Test Symposium (VTS) 2008, San Diego California, USA, 27th April 2008
  5. Costas Argyrides, Fabian Vargas, Dhiraj Pradhan, Merging Built-in Current Sensor with H-Tree Architecture for SRAM Reliability Improvement, Proceedings of IEEE Latin American Test Workshop (LATW), Puebla Mexico, 17-20 February 2008.
  6. J. Mathew, Costas Argyrides, A. M Jabir, D. K. Pradhan “Single Error Correcting Finite Field Multipliers over GF(2m)”, Proceedings of 21st Conference on VLSI Design (VLSI 08), Hyderabad, India, 4-8 Jan 2008

For more details on my work and my publications visit my website at