NANOSIL - Silicon-based nanostructures and nanodevices for long term nanoelectronics applications
The Warwick group were instrumental in setting up the European Network of Excellence in Silicon-based Nanodevices (SiNANO) and its successor project NANOSIL, which runs from January 2008 to December 2011 and is funded by the European Commission under the seventh EU Framework Programme (FP7) for Research and Technological Development. It is coordinated in Grenoble through CNRS by Francis Balestra,
with Evan Parker as Deputy Coordinator and leader of "More Moore" activity - one of the two principal workpackages.
NANOSIL aims to integrate the excellent European research laboratories and capabilities at the European level in order to strengthen scientific and technological excellence in the field of nanoelectronic materials and devices for terascale integrated circuits (ICs). It will explore and assess the science and technological aspects of nanodevices and operational regimes relevant to the 22nm technology node and beyond. Thus providing a forward-look for the industry, enabling informed decisions to be taken on technology development to speed up technological innovation.
There are seven Flagship Projects in the areas of nanoscale CMOS (WP1) and post-CMOS (WP2), known as the “More Moore” and “Beyond-CMOS” domains. This work will be carried out through a network of joint processing, characterisation and modelling platforms. Alongside these technological Flagship Projects each workpackage also has a Visionary Project that will act as a forum to explore novel ideas bewteen academia and European industry. Support for the operation of the Flagship Projects comes from WPs in Processing, Modelling and Characterisation, and Integration and spreading of excellence.
Warwick are involved in:
- coordinating the research work across all 28 partners
- driving WP1 (More Moore)
- supplying epitaxial material to the Joint Processing Platform
- specific research work on the Flagship Project 1.1
Appraisal of new channel materials for end of CMOS era, whose objectives are:
To fabricate and investigate new channel materials enabling enhanced mobilities and to assess their properties when transferred to insulator platforms.
Specifically to identify the material, platform design, crystallographic orientation, channel direction, layer thickness and strain that maximises electron and hole mobility.
PULLNANO - Pulling the limits of nanoCMOS electronics
PullNano was a 45 million euro FP6 Integrated Project, led by Europe's major semiconductor companies, that followed from the NANOCMOS IP and SINANO NoE and ran from 2006 to 2008. This project brought together the best of European nanoelectronics research and incorporated the Crolles 2 Alliance, technology institutes such as IMEC and LETI, and a number of academic teams organised in clusters. It aimed to both produce a feasibility demonstration of an aggressively scaled 32nm node SRAM chip and to prepare the materials, architectures and devices for the 22nm node.
The universities in the project were principally looking at a number of possible future technologies that could be incorporated in the 22nm node. Warwick's tasks included:
- Low threading defect density virtual substrates
- Introduction of tensile strain by carbon containing source/drain contacts
- Globally strained on-insulator platforms, via layer transfer
SiNANO aimed to strengthen European scientific and technological excellence in the field of electronics, Si-based nanodevices for terascale integrated circuits. The Network gathered together 46 universities, research centers and enterprises, coming from 16 European countries and representing more than 300 researchers and PhD students. As a result of this network many new research collaborations have been established and an efficient Joint Processing Facility of small University facilities has been established. It is expected that durable integration of the key partners will continue well beyond the initial 3 year project.
SiNANO ran from January 2004 to December 2006 and was funded by the European Commission under the sixth EU Framework Programme (FP6) for Research and Technological Development. It was coordinated in Grenoble through CNRS by Francis Balestra, with David Leadley and Evan Parker sitting on the central Executive and Scientific Committee. Warwick led the major workpackage on New Channel Materials for Ultimate CMOS.
This work package (WP1) aimed to produce CMOS device performance improvements of real consequence at, and beyond, current technology nodes through modification of the Si channel material, by imposition of strain and/or addition of other group IV elements (Ge and C), whilst remaining compatible with Si processing. WP1 consisted of four device-led activities: (i) advancing strained silicon technologies; (ii) approaches to strain platforms; (iii) SiGe channel devices and (iv) devices with C containing channels.
HMOS - SiGe for MOS Technologies
Warwick initiated and led an EPSRC funded research programme concerned with developing SiGe for MOS Technologies and applications that included 13 research teams, from 9 UK universities along with industrial partners Synergetic, Daimler-Chrysler, Infineon Technologies and XFAB (several company names have changed since).
The £7M programme, known affectionately as "HMOS" for heterostructure MOS, ran from 1997 to 2004 and really launched the UK SiGe programme on to the world scene.
Following the successful EPSRC initiative in SiGe, including the above HMOS program and a simialar project on SiGe HBTs, this Network was established to strengthen the whole UK silicon community and determine how best to utilise and exploit this country's inherent talent in this discipline. It is particularly relevant to discus these issues at a time when simple CMOS scaling is being replaced in future technology generations by extensive research on new materials, such as SiGe and new architectures, such as SOI, and silicon-based technologies are being developed for new applications, such as microsystems, silicon-based photonics and bioMEMS.
Support from EPSRC enabled the group's MBE system to be upgraded in 2004.