Dr Vishal Shah
2017-Present: Associate Professor, School of Engineering, University of Warwick, UK
- 2021-2024 PI on £400k EPSRC grant (EP/W004291/1): TESiC-SuperJ - Trench Epitaxy for SiC Superjunctions
- 2021-2024 CI on £975k EPSRC grant (EP/V028596/1): Electric Fields by 4D scanning transmission electron microscopy
- 2021-2024 CI on £740k EPSRC grant (EP/V000543/1): Silicon Carbide Power Conversion for Telecommunications Satellite Applications
- 2017-2021 PI on £700k EPSRC Fellowship (EP/P017363/1): Ultra-high voltage (>30KV) power devices through superior materials for HVDC transmission (Wide Bandgap Epitaxy - SiC)
2015-2017: Research Scientist, Mantis Deposition, Thame, UK
- Developed deposition tools and techniques for epitaxy, sputtering, ebeam evaporation, ion bombardment, nano-particle deposition etc.
2013-2015: Senior Research Fellow, School of Engineering, University of Warwick, UK
- Led the technical installation and management of a £2.3m cross-disciplinary laboratory.
- Senior researcher in a team consisting of 2 research staff and 6 PhD students within the "Underpinning Power Electronics: Devices Theme" (EP/L007010/1) project.
- Used results from multiple source data analysis to secure funding for research, securing £240k worth of time at a national facility.
2009-2013: Research Fellow, Department of Physics, University of Warwick U.K.
- Worked on the the "mK-project" (EP/F040784/1) and "platform grant" (EP/J001074/1) teams, with 2 PhD students and 10 undergraduate projects.
- 2005-2009: Ph.D Physics, University of Warwick
Industrial Experience and Placements
- 2015-2017: Honorary Fellow at Warwick University
- 2011-2015: Visiting user at the Diamond Light Source, UK
- 2011-2013: Visiting researcher at Aalto University
- 2010-2013: Visiting researcher at VTT Technical Research Centre of Finland
- 2007: Visiting researcher at Stuttgart University.
3C, 4H and 6H-SiC Power devices and CVD Epitaxy: As a major collaboration between the UK SiC community of Warwick, Newcastle, Cambridge and Bristol, this project is essentially based around the epitaxy of thick (>50µm) SiC layers for high power devices for rectifiers and inverters. Alongside the epitaxy of SiC power device I participate in the fabrication of PiN diodes, MOSFETs and trench MOSFETs in house. I am a PI on a £720k EPSRC fellowship EP/P017363/1.
Si and Ge epitaxy upon SiC substrates: In collaboration with the Power Electronics, Applications & Technology in Energy Research (PEATER) group at Warwick Uni. The investigation focuses on the deposition of doped Si and Ge on SiC substrates to create layers to be used in high temperature electronics. This on-going investigation has involved a close collaboration with P.M.Gammon and the NICHE project, funded by the Royal Academy of Engineering.
Reverse Graded Virtual Substrates (RGVS): This investigation was the main focus for my thesis doctorate. The resulting buffers were novel and state-of-the-art, competing with the best buffers available. This research is funded by the Ge Renaissance program (EP/F031408/1) and the Si Photonics program (EP/E065317/1).
Strained Ge heterostructures on RGVSs for device applications: This work was performed in conjunction with work carried out for the reverse graded substrates, and has recently resulted in ultra-high carrier mobility structures, this research is still on-going. This research was funded by EPSRC grant EP/D034485/1.
Ge on AlGaAs for Spintronic applications: This work is being performed in collaboration with Cavendish Laboratory and Toshiba Research Group to demonstrate spin transport in germanium. I have performed the MBE growth of these layers and also performed extensive physical characterisation of the Ge/AlGaAs material system, this work helped start the spintronics research under research grant (EP/J003263/1).
Doped Si and Ge for millikelvin applications: This area of research was in collaboration with Cardiff University, Royal Holloway University and VTT and Aalto University (both from Helsinki). The aim of which is to demonstrate effective sub-kelvin cooling in Semiconductor/Superconductor structures, aimed to replace dilution cryogenics and to demonstrate applications. This programme was funded by EPSRC grant EP/F040784/1 and also EU FP7 Nanofunction Network of Excellence
MEMS for cooltronics applications: This area of research is in conjunction with research upon Semiconductor/Superconductor junctions. Due to the low power of the cooling junctions they are required to be isolated from the main substrate. To this end they must be placed upon platforms which have a minimal volume and physically disconnected in a vacuum, meaning MEMS fabrication for suspended structures. Work from this programme has been submitted under two British patent applications: 1107574.4 and 1206913.4. This programme was funded by EPSRC grant EP/J001074/1.
Projects and Grants
|Title||Funder||Award start||Award end|
|Silicon Carbide Power Conversion for Telecommunications Satellite Application||EPSRC||01 Apr 2021||30 Sep 2024|
|Ultra High Voltage (>30KV) Power Devices Through Superior Materials For HVDC Transmission (EPSRC Postdoctoral Fellowship)||EPSRC||01 Jul 2017||20 Jan 2021|
|Creating Sillicon Based Platforms for New Technologies (Platform Grant)||EPSRC||01 Mar 2012||28 Feb 2017|
The PEATER Group is one of the leading research groups in the world focused on SiC device development, with a suite of equipment and facilities to match. This includes:
- The Science City Cleanroom, a 150 m2 ISO class 6 cleanroom including high temperature oxidation and annealling furnaces, photolithography, etching and wet processing, metal deposition, and atomic layer deposition.
- The UK’s only industrial SiC CVD reactor in an ISO class 4 cleanroom, used for the epitaxial growth of SiC.
Characterisation Facilities, including a Keysight B1505A power device analyser and a SemiProbe semi-automated wafer prober for device characterisation up to 10 kV, 100 A and 300 °C.
An ISO class-8 packaging cleanroom.