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Dr Vishal Shah

Dr Vishal Shah

Associate Professor 

vishal dot shah at warwick dot ac dot uk
+44 (0) 24 7657 5467

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Dr Vishal Shah; Associate Professor, joined the School of Engineering at the University of Warwick in 2017 and is part of the PEATER group (Power Electronics Applications and Technology in Energy Research). He has been working in the (ultra) wide bandgap (UWBG) materials research activity and his research interests are driven by the application-led materials development. He has over 15 years’ experience developing semiconductor materials and technologies for numerous application areas including power electronics, quantum technology, photovoltaics, CMOS, MEMS and sensing. He runs the Warwick fabrication cleanroom and also the UK’s only Silicon Carbide (SiC) epitaxial facility at Warwick. He has written 3 patents, and published 44 journal papers, 48 conference papers, four book chapters and made over 75 conference contributions, with an h-index of 18 and over 1213 citations (Google Scholar) as of July 2023. He is PI on a combined grant portfolio of £1.2M and CI on additional grants worth £2.5M.

2017-Present: Associate Professor, School of Engineering, University of Warwick, UK

  • Established a Wide Bandgap Materials Laboratory, currently focussing on Silicon Carbide application-led materials development.

2015-2017: Research Scientist, Mantis Deposition, Thame, UK

  • Developed deposition tools and techniques for epitaxy, sputtering, ebeam evaporation, ion bombardment, nano-particle deposition etc.

2013-2015: Senior Research Fellow, School of Engineering, University of Warwick, UK

  • Senior researcher in a team consisting of 2 research staff and 6 PhD students within the "Underpinning Power Electronics: Devices Theme" (EP/L007010/1) project.

2009-2013: Research Fellow, Department of Physics, University of Warwick U.K.

  • Worked on the the "mK-project" (EP/F040784/1) and "platform grant" (EP/J001074/1) teams, with 2 PhD students and 10 undergraduate projects.

Research Interests

4H-SiC Power devices and CVD Epitaxy: As a major collaboration between the UK SiC community of Warwick, Newcastle, Cambridge and Bristol, this project is essentially based around the epitaxy of thick (>50µm) SiC layers for high power devices for rectifiers and inverters. Alongside the epitaxy of SiC power device I participate in the fabrication of PiN diodes, MOSFETs and trench MOSFETs in house. I was a PI on a £720k EPSRC fellowship EP/P017363/1 and am developing 3D 4H-SiC epitaxy (EP/W004291/1)

Use of 3C, 4H and 6H-SiC materials in "More the Moore" applications: This work is ongoing where we are implementing other technologies using SiC knowledge from power electronics: such as SiC for functional coatings (Innovate UK, 10073941)), using SiC for photoelectrochemical generation of hydrogen from water splitting (funded from EPSRC EP/X527257/1), developing semi-insulating SiC for GaN integration for RF applications (CSHubJFS13 through EP/P006973/1), using 3C SiC as a MEMS material, developing material for SiC sensors etc.

Analysis and reduction of defects in semiconductors: We are developing new techniques for the detection of, reduction and utilisation of defects. For example, together with the Diamond Light Source we are developing non-destructive X-ray Diffraction Topography of materials and devices. In addition, we are developing DLTS measurement of point defects in either for use in quantum applications, or improve the efficiency of power electronics.

Si and Ge epitaxy upon SiC substrates: In collaboration with the Power Electronics, Applications & Technology in Energy Research (PEATER) group at Warwick Uni. The investigation focuses on the deposition of doped Si and Ge on SiC substrates to create layers to be used in high temperature electronics. This on-going investigation has involved a close collaboration with P.M.Gammon and the NICHE project, funded by the Royal Academy of Engineering.

Reverse Graded Virtual Substrates (RGVS): This investigation was the main focus for my thesis doctorate. The resulting buffers were novel and state-of-the-art, competing with the best buffers available. This research is funded by the Ge Renaissance program (EP/F031408/1) and the Si Photonics program (EP/E065317/1).

Strained Ge heterostructures on RGVSs for device applications: This work was performed in conjunction with work carried out for the reverse graded substrates, and has recently resulted in ultra-high carrier mobility structures, this research is still on-going. This research was funded by EPSRC grant EP/D034485/1.

Doped Si and Ge for millikelvin applications: This area of research was in collaboration with Cardiff University, Royal Holloway University and VTT and Aalto University (both from Helsinki). The aim of which is to demonstrate effective sub-kelvin cooling in Semiconductor/Superconductor structures, aimed to replace dilution cryogenics and to demonstrate applications. This programme was funded by EPSRC grant EP/F040784/1 and also EU FP7 Nanofunction Network of Excellence

MEMS for cooltronics applications: This area of research is in conjunction with research upon Semiconductor/Superconductor junctions. Due to the low power of the cooling junctions they are required to be isolated from the main substrate. To this end they must be placed upon platforms which have a minimal volume and physically disconnected in a vacuum, meaning MEMS fabrication for suspended structures. Work from this programme has been submitted under two British patent applications: 1107574.4 and 1206913.4. This programme was funded by EPSRC grant EP/J001074/1.

Projects and Grants

Selected Publications

For up to date lists please consult my Google Scholar, Scopus or ORCID

Research Facilities

The PEATER Group is one of the leading research groups in the world focused on SiC device development, with a suite of equipment and facilities to match. This includes:

  • The Science City Cleanroom, a 150 m2 ISO class 6 cleanroom including high temperature oxidation and annealling furnaces, photolithography, etching and wet processing, metal deposition, and atomic layer deposition.
  • The UK’s only industrial SiC CVD reactor in an ISO class 4 cleanroom, used for the epitaxial growth of SiC.
  • Characterisation Facilities, including a Keysight B1505A power device analyser and a SemiProbe semi-automated wafer prober for device characterisation up to 10 kV, 100 A and 300 °C.

  • An ISO class-8 packaging cleanroom.


ES434 - ASICS, MEMS and Smart Devices

ES3E6 - Microwave Engineering and RF Circuits

ES2D6 - Semiconductor Materials and Devices