I am Technical Program Co-Chair for the 27th International Conference on Field-Programmable Logic and Applications, FPL 2018, alongside Miriam Lesser and Michaela Blott. I previously served as Program Chair for the 26th International Conference on Microelectronics, ICM 2014, the 5th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2015, and the 27th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2016. I chaired the Applications Track at FPL 2009, and launched the Demo Track at FPT in 2009.
I serve on the Technical Programme Committees of a number of renowned international conferences in my field including:
- International Conference on Field Programmable Logic and Applications (FPL)
- TPC Member 2008, 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016, 2017
- Applications Track Chair 2009
- Reviewer 2004, 2005, 2006, 2007
- IEEE International Conference on Field Programmable Technology (FPT)
- TPC Member 2009, 2010, 2011, 2012, 2013, 2014, 2015, 2016
- Demonstrations Chair 2009, 2010, 2011, 2012, 2014
- Publicity Chair 2011
- IEEE International Symposium on Field Programmable Custom Computing Machines (FCCM)
- TPC Member 2013, 2014, 2015, 2016, 2017
- ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA)
- TPC Member 2017
- Design, Automation, and Test in Europe Conference (DATE)
- TPC Member 2015, 2016, 2017
- Design Automation Conference (DAC)
- Expert Reviewer (TPC Member) 2011, 2012, 2013
- Reconfigurable Architectures Workshop (RAW)
- TPC Member 2011, 2012, 2013, 2015, 2016
- IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP)
- TPC Member 2013, 2014, 2015, 2016
- International Symposium on Applied Reconfigurable Computing (ARC)
- TPC Member 2009, 2010, 2011, 2012, 2013
- Architectures Track Chair, Publicity Chair 2011
- International Conference on Reconfigurable Computing and FPGAs (ReConFig)
- TPC Member 2008, 2009, 2010
- Communications and DSP Track Chair 2008, 2009
- Cyber Physical Systems Track Chair 2010
- Reconfiguration Techniques Trach Chair 2016
- Irish Signals and Systems Conference (ISSC)
- TPC Member 2008
I have also reviewed papers for various other conferences including ISVLSI, DSD, among others.
I have served on the Editorial Board of the IET Computers and Digital Techniques and International Journal of Reconfigurable Computing (IJRC).
I also regularly review for a number of international journals including:
- ACM Transactions on Design Automation of Electronic Systems
- ACM Transactions on Embedded Computing Systems
- ACM Transactions on Reconfigurable Technology and Systems
- IEEE Design & Test of Computers
- IEEE Embedded Systems Letters
- IEEE Journal on Selected Areas in Communications
- IEEE Transactions on Circuits and Systems I
- IEEE Transactions on Circuits and Systems for Video Technology
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- IEEE Transactions on Computers
- IEEE Transactions on Image Processing
- IEEE Transactions on Mobile Computing
- IEEE Transactions on Signal Processing
- IEEE Transactions on VLSI
- IET Circuits, Devices and Systems
- IET Computers and Digital Techniques
- International Journal on Reconfigurable Computing
- Journal of VLSI Signal Processing
- Journal of Real-Time Image Processing
- Journal of Systems Architecture
- EURASIP Journal on Embedded Systems
- Microprocessors and Microsystems
I have given a number of invited talks related to my research including the following:
- FPGA Virtualisation for Connected Accelerators, IBM Reseach Labs, Zürich, Switzerland, August 2016.
- Architecture Centric Overlays for Abstraction and Performance, Future of REconfigurable Systems and their High-level design (FRESH) Summit, London, UK, July 2016.
- Fast FPGA Tool Flows with Overlays, Workshop on Arduino-like Fast-Start for FPGAs at FCCM 2016, Washington, DC, May 2016.
- Research Directions for FPGAs in the Cloud, Huawei Research, Toronto, Canada, June 2015.
- Efficiency Across Scales of Computing with Adaptive Hardware, King Abdullah University of Science and Technlogy (KAUST), Saudi Arabia, March 2015.
- Architectural Heterogeneity: Augmenting the Cloud and Securing the Connected World, Qatar Computing Research Institute, Doha, Qatar, June 2014.
- Mapping Dynamic Cognitive Radios to Hybrid FPGA Architectures, Electrical and Computer Engineering Department, Northeastern University, MA, May 2014.
- Reconfigurable Computing Research at NTU, Xilinx Inc., San Jose, CA, February 2014.
- The Many Lives of an FPGA DSP Block, Department of Electrical and Electronic Engineering, Imperial College London, January 2014.
- Using FPGA DSP Blocks for More Than DSP, Electrical and Computer Engineering Department, Texas A&M University at Qatar, Doha, Qatar, July 2013.
- Programmability of Reconfigurable Architectures, Chinese University of Hong Kong, City University of Hong Kong, and University of Hong Kong, March 2013.
- Modelling and Implementation of FPGA-Based Cognitive Radios, Computer Science and Artificial Intelligence Lab (CSAIL), Massachusetts Institute of Technology (MIT), Cambridge, MA, June 2010.
- Partial Reconfiguration and the Advent of Adaptive Hardware, School of Information Technology, International University in Germany, Bruchsal, Germany, September 2008.
- Efficient Implementation of the Trace Transform, Sony Broadcast and Professional Research Labs, Basingstoke, UK, September 2006.
- From Algorithm to Architecture, Xilinx Inc., Dublin, Ireland, July 2006.
I am a Senior Member of the IEEE, including Circuits and Systems and Computer Societies.
I am a Senior Member of the ACM, including ACM SIGBED and SIGDA.
I am also a Member of the IET.