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Academic Service

Conferences

I am Co-Chair of the Reconfigurable Computing (D11) Topic for the Design, Automation, and Test in Europe Conference. I was previously Technical Program Co-Chair for the 27th International Conference on Field-Programmable Logic and Applications, FPL 2018, alongside Miriam Lesser and Michaela Blott, and Technical Program Chair for the 27th Annual IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2016, the 5th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, HEART 2015, and the 26th International Conference on Microelectronics, ICM 2014. I chaired the Applications Track at FPL 2009, and launched the Demo Track at FPT in 2009.

I serve on the Technical Programme Committees of a number of renowned international conferences in my field including:

I have also reviewed papers for various other conferences including ISVLSI, DSD, among others.

Journals

I have previously served on the Editorial Board of the IET Computers and Digital Techniques and International Journal of Reconfigurable Computing (IJRC).

I also regularly review for a number of international journals including:

  • ACM Transactions on Design Automation of Electronic Systems
  • ACM Transactions on Embedded Computing Systems
  • ACM Transactions on Reconfigurable Technology and Systems
  • IEEE/ACM Transactions on Networking
  • IEEE Design & Test of Computers
  • IEEE Embedded Systems Letters
  • IEEE Journal on Selected Areas in Communications
  • IEEE Transactions on Circuits and Systems I
  • IEEE Transactions on Circuits and Systems for Video Technology
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • IEEE Transactions on Computers
  • IEEE Transactions on Image Processing
  • IEEE Transactions on Mobile Computing
  • IEEE Transactions on Parallel and Distributed Systems
  • IEEE Transactions on Signal Processing
  • IEEE Transactions on VLSI
  • IET Circuits, Devices and Systems
  • IET Computers and Digital Techniques
  • International Journal on Reconfigurable Computing
  • Journal of VLSI Signal Processing
  • Journal of Real-Time Image Processing
  • Journal of Systems Architecture
  • EURASIP Journal on Embedded Systems
  • Microprocessors and Microsystems

Invited Talks

I have given a number of invited talks related to my research including the following:

  • Reconfigurable Computing Research at Warwick, invited talk at Xilinx Research Labs, Singapore, July 2018.
  • FPGA Overlays: Enhancing Abstraction and Productivity, keynote talk at 13th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), Lille, France, July 2018.
  • Distributed Heterogeneous Computing and the Role of FPGAs, National University of Singapore, Singapore, April 2018.
  • Enhancing Abstraction and Productivity with FPGA Overlays, University of Hong Kong, Hong Kong, April 2018.
  • Next Generation Automotive Networks for ADAS and Autonomy, Workshop on Reconfigurable Computing (WRC) at HiPEAC 2018, Manchester, UK, January 2018.
  • Virtualising Distributed Accelerators in Networked Systems, Trinity College Dublin, Ireland, October 2017.
  • In-Network Connected Compute with FPGAs, TechWorks High Performance Digital Systems and Applications Day, Coventry, UK, September 2017.
  • Exploring the Potential for FPGA Scientific Computing Research, Warwick Centre for Predictive Modelling Seminar Series, Coventry, UK, January 2017.
  • FPGA Virtualisation for Connected Accelerators, IBM Reseach Labs, Z├╝rich, Switzerland, August 2016.
  • Architecture Centric Overlays for Abstraction and Performance, Future of REconfigurable Systems and their High-level design (FRESH) Summit, London, UK, July 2016.
  • Fast FPGA Tool Flows with Overlays, Workshop on Arduino-like Fast-Start for FPGAs at FCCM 2016, Washington, DC, May 2016.
  • Research Directions for FPGAs in the Cloud, Huawei Research, Toronto, Canada, June 2015.
  • Efficiency Across Scales of Computing with Adaptive Hardware, King Abdullah University of Science and Technlogy (KAUST), Saudi Arabia, March 2015.
  • Architectural Heterogeneity: Augmenting the Cloud and Securing the Connected World, Qatar Computing Research Institute, Doha, Qatar, June 2014.
  • Mapping Dynamic Cognitive Radios to Hybrid FPGA Architectures, Electrical and Computer Engineering Department, Northeastern University, MA, May 2014.
  • Reconfigurable Computing Research at NTU, Xilinx Inc., San Jose, CA, February 2014.
  • The Many Lives of an FPGA DSP Block, Department of Electrical and Electronic Engineering, Imperial College London, January 2014.
  • Using FPGA DSP Blocks for More Than DSP, Electrical and Computer Engineering Department, Texas A&M University at Qatar, Doha, Qatar, July 2013.
  • Programmability of Reconfigurable Architectures, Chinese University of Hong Kong, City University of Hong Kong, and University of Hong Kong, March 2013.
  • Modelling and Implementation of FPGA-Based Cognitive Radios, Computer Science and Artificial Intelligence Lab (CSAIL), Massachusetts Institute of Technology (MIT), Cambridge, MA, June 2010.
  • Partial Reconfiguration and the Advent of Adaptive Hardware, School of Information Technology, International University in Germany, Bruchsal, Germany, September 2008.
  • Efficient Implementation of the Trace Transform, Sony Broadcast and Professional Research Labs, Basingstoke, UK, September 2006.
  • From Algorithm to Architecture, Xilinx Inc., Dublin, Ireland, July 2006.

Memberships

I am a Senior Member of the IEEE, including Circuits and Systems and Computer Societies.

I am a Senior Member of the ACM, including ACM SIGBED and SIGDA.

I am also a Chartered Engineer and Member of the IET.