Beniel Thileepan
About Me
I am a 2nd year PhD student at the Department of Computer Science, reading my PhD in High Performance Computing. I am supervised by Prof. Gihan Mudalige and Assoc. Prof. Suhaib Fahmy.
Prior to my PhD studies, I worked as a senior hardware accelerated engineer for the London Stock Exchange Group Technology (LSEG Technology) as a research engineer in high-performance GPU, FPGA accelerated fintech and quant computing solutions from 2019 to 2022.
I obtained my Bachelor of Science in Engineering (Hons) degree in 2019 from the University of Moratuwa, Sri Lanka and worked as a research intern in the Augmented Human Lab, SUTD, Singapore under the supervision of Assoc. Prof. Suranga Nanayakara in 2017.
Research
My research work is on the source-to-source code translation to a High-Level-Synthesis(HLS) based Field Programmable Array (FPGA) language from a Domain-Specific Language (DSL). Currently, I am focusing on OPS-DSL, a domain-specific language that supports multigrid structured mesh stencil computations and source-to-source code translation techniques to HLS and optimization.
Publications
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Sumanasena, V., Fernando, H., de Silva, D., Thileepan, B., Pasan, A., Samarawickrama, J., Osipov, E., & Alahakoon, D. (2023). Hardware Efficient Direct Policy Imitation Learning for Robotic Navigation in Resource-Constrained Settings. https://doi.org/10.3390/s24010185
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Teaching Activities
For 2022/2023:
For 2023/2024:
Additionally, I have been taking part in exam invigilation duties.
Leadership Roles
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- WPCCS 2023 Winter Co-Chair (Current)
- CPS Network - Committee Member (Current)
Contact
beniel.thileepan@warwick.ac.uk
MB4.17, Mathematical Science Building, University of Warwick.
Linkedin: thileepan-beniel
GitHub: benielT